1. Field of the Invention
The present invention relates to a sub-circuit that regulates in a control system the phase difference used to synchronize two signals that are not in phase. In particular, the present invention relates to a sub-circuit for limiting the pulse width of a phase-difference signal used to operate a synchronizing device of the control system. More particularly, the present invention relates to a sub-circuit that provides a gradual transition in the change in frequencies developed at the output of a phase-locked loop (PLL) circuit. The sub-circuit provides a means for increasing or decreasing the transition time for changing from one operating frequency to another in order to maintain synchronization of circuitry connected to the PLL circuit when such a transition occurs. Still more particularly, the present invention is related to a phase-error-limiting circuit that is designed to modify the width of the UP and DOWN pulses transmitted to a PLL circuit charge pump so as to regulate the current available for operating a PLL circuit voltage-controlled oscillator when the phase difference between a reference signal and the output of the voltage-controlled oscillator exceeds a preselected value.
2. Description of the Prior Art
In the field of personal computers there is increasing emphasis on the need to manage the power consumed during operation. This is particularly true in the world of laptop and hand-held computers where access to standard 110-Volt AC power supplies is not essential. It is well known that a variety of methods for enhancing power consumption efficiency have been developed, including, but not limited to, increasing the efficiency or size of a DC power pack, reducing the size of the components of the device and/or placing the device in a "sleep" mode during periods of intermittent inactivity. The latter is typically achieved by reducing the clock rate of the computer. That is, if the design operating frequency of the computer is 66 MHz for example, more dynamic power is consumed if all circuitry remains at that frequency. However, if the clock rate for such a computer can be reduced to 32 MHz during inactivity, less power is consumed and the service life of the DC power pack is extended. Under this method of operation it is necessary to provide circuitry that locks the frequency of one signal to the frequency of another signal so that sub-circuitry that might otherwise be operating at different signal frequencies are synchronized. Failure to provide such synchronization can result in code execution failure, improper turning on or turning off of buses, etc. While there are countless control systems designed to provide synchronization, one type in particular is phase-locked loop (PLL) circuitry.
The basic operation of PLL circuitry can be described with reference to prior art drawing FIG. 1. In that drawing it can be seen that a simple PLL includes an Input Counter for receiving an input signal. The input signal is typically the reference signal obtained from a crystal oscillator and to which "downstream" circuitry is to be synchronized. The input signal is transmitted from the Input Counter to a phase-frequency detector (PFD) that compares the input signal to an output signal generated by a voltage-controlled oscillator (VCO) and transmitted by a Feedback Counter. The PFD transmits to a Charge Pump an UP or DOWN signal of duration comparable to the phase difference between the reference input signal and the VCO output signal. That is, the width of the pulse of the UP or DOWN signal is a function of the phase difference between the two signals. An UP signal only from the PFD operates to charge a Filter and a DOWN signal only from the PFD operates to discharge the Filter. When both UP and DOWN signals are set, the Charge Pump provides no current to the Filter. The Filter conducts the alternating current (AC) component of the PFD signal away from the VCO, leaving only the direct current (DC) component transmitted to the VCO. The magnitude of the DC signal transmitted to the VCO is ordinarily a function of the phase difference between the original input signal and the VCO output signal to the PFD. That is, as the phase difference increases, the change in average current supplied to the Filter increases. As is well known, a change in the magnitude of the DC signal to the VCO operates to change the frequency of the VCO output signal until the output signal and the input signal are of essentially the same frequency. In many PLL systems, as the phase difference between the two signals increases, the voltage applied to the VCO increases proportionally such that large phase differences may induce more quickly the change in the frequency of the VCO signal.
While the present discussion is directed to PLL circuitry, it is to be understood that many other control systems may operate in a similar fashion. That is, many such control systems operate on the general principle of comparing a reference signal and a feedback signal, generating an error signal based on the difference in the two compared signals, and modifying an output signal based upon that error signal. In the case of a PLL, that error signal is related to phase. In other control systems, that error signal may be voltage related, current related, position related, etc. Regardless of the specific type of error signal, it is the comparison of the input reference signal and the feedback signal, which may be the output signal, or at least determined by the output signal, that is used to effect a change in the control system in order to bring the output signal in line, or "locked" on to the input reference signal.
The switching times of devices used in present systems, such as the laptop computers that are presently available, are much faster than those used only a few years ago, and the trend is for ever faster and smaller systems. The PLL devices available to provide the synchronization necessary in such systems are correspondingly smaller and faster. Unfortunately, the small complex systems that are and that will soon be available include many components, not all of which operate at the same speed. This is particularly the case where it is desirable to conserve energy when the system is not in use and yet certain components must be kept operating. For example, in a computer system designed to operate in the range 50-66 MHz, some components, such as timing clocks, can be maintained at much lower rates, on the order of 32 MHz and less, when the computer is not in use, so as to conserve power. However, problems in synchronization can occur when the PLL is designed to meet the synchronization needs for output frequencies in the higher range. That is, the PLL may too quickly convert from a higher to a lower frequency before downstream components are prepared to accept the altered input. In one example, a downstream component that requires a delay on the order of milliseconds before receiving the changed input frequency may be coupled to a PLL that switches from one frequency to another within a few microseconds. The timing difference may well cause a loss of lock in devices with PLL-based timing elements, including, but not limited to, CPUs and keyboard controllers.
One method for delaying the switched output of the PLL shown in FIG. 1 would be to modify the prior Filter so as to slow the signal transmitted to the VCO. That may be done by increasing the capacitance of the Filter, either with an internal capacitor (one that is "on-chip"), or with an external capacitor (a discrete "off-chip" device). To get the timing delay previously indicated, the capacitance would have to be much greater than that used for most of the present PLL circuits needed to switch in the high frequency range. That is, one or more capacitors valued in the microfarad range would be needed, rather than the picofarad capacitors ordinarily used. In the field of monolithic integrated circuits, where space on a chip is extremely limited, the addition of one or more very large microfarad-sized internal capacitors would severely restrict a circuit designer's options with regard to other components. It would also increase the cost of the chip. Since the ongoing goal is to make more efficient devices, the addition of more and larger elements, can be viewed as a step backward and therefore undesirable. Similarly, if an external capacitor were used, there would be a resultant reduction in available board space and an increase in board cost.
In all of this discussion regarding the timing problems that are not completely addressed by the PLL circuitry presently available, the primary characteristics of the PLL must be kept in sight when looking for a solution. In particular, the specified gain and operating bandwidth of the PLL must be maintained. The operating bandwidth selected and to be maintained by the PLL is dependent upon the need to avoid the effects of jitter caused by noise external to the circuit. A PLL that operates within the band of interest as expected and with the gain desired, and that provides the type of transition delay noted would be particularly useful. Similarly, this would be useful for other types of control systems, including clock recovery circuits, floppy disk controllers, or any system that incorporates the comparison of a reference signal and a particular output signal that is fed back to a phase-difference-determining component.
Therefore, what is needed is a means for regulating or otherwise modifying a phase difference signal in a control system so as to regulate the rate at which synchronization of at least two signals is achieved. In particular, what is needed is a PLL device that provides for synchronization of two signals initially unequal in frequency in a predetermined bandwidth and that also slows the transition from one frequency to another within the predetermined bandwidth. What is also needed is a PLL device as noted that does not interfere with the standard operation of the system and that does not increase or otherwise affect the jitter associated with the system. Still further, what is needed is a PLL device as noted that may be fabricated as part of a monolithic circuit with minimal increase in the space required.